· Fin dimension variability
Fin height and
width can have strong impact on device performance variability. Of the two, fin
height variation is generally more critical 18. Device’s effective electrical
width is directly related to fin height. Hence, any fin height variation due to
variation of fin forming processes directly transfers to device width
variation. In contrast to planar devices, where active area patterning
variation affects only the narrowest of transistors, all fin-based devices
suffer from the same percentage of device width error 18. This variability is
primarily related to definition of fin height by STI dielectric recess process
after polishing planarization and can reach several percent of every device
FinFET channel is
usually desired to be fully depleted however to have better control of leakage
current under the fins the channel is usually lightly doped 10. The doping concentration
of Source/Drain region requires high dopant and hence increases the series
resistance of the device 18. This damages the fin’s geometry of the device.
To overcome this problem in-situ epitaxial growth is done at the source and drain
area with or without removing the fin of the structure 18.
FinFETs has more
parasitic capacitance than planar structures. The overlap between the front and
back gate increases the capacitance of the device. The variation in the Fin
height, i.e. the increase in fin height and decrease in fin pitch reduces the
capacitance of the device 10.